As the size of memory systems increase, it becomes advantageous to configure the memory system to have at least one redundant bit which is available to replace a defective bit in the memory system. For example, a memory system such as a static random access memory (“SRAM”) will have circuitry forming multiple bits which form the memory system. If any of the bits are defective at the end of the manufacturing process, the memory system will not function properly. Accordingly, it is advantageous for a redundant bit to be formed during the formation of the main memory, where the redundant bit is configured so that it can substitute for a defective bit of the memory system. Thus, the memory system having a defective bit will still function properly due to substitution of the redundant bit for the defective bit.
As memory systems become larger and incorporate more bits, the number of available redundant bits is increased to accommodate a larger number of potential defective bits. But, in such known types of memory structure, a redundant bit is available to replace only a certain number of bits in a memory system. This certain number of bits is referred to as a redundant region. Accordingly, in some memory systems, a particular redundant bit can replace a bit only in its corresponding redundant region. This is akin to a “static” system.
Alternatively, certain memory designs allow for row redundancy. Row redundancy is a memory system configuration where a redundant row is created and is able to replace a defective row in the memory system. Typical memory system configurations allow a redundant row to replace any row of a memory system. Furthermore, a memory system can have multiple redundant rows and each one of those redundant rows can replace any defective row in the memory system. However, an entire row must be replaced in such configurations.
It should also be noted that a non-compilable memory allows the memory designer to pre-determine the size of a redundant region and because the size of the memory does not vary, that redundant region will be fixed. However, for a compilable memory, the size of the memory is not fixed and thus, virtually any size memory up to a prescribed limit may be formed. Accordingly, a simplified method for configuring the redundant regions of a compilable memory with varying memory size, such as a SRAM is needed.
Bit redundancy has been utilized in compiled SRAMs, though. In these configurations, one redundant bit is provided per compiled memory. The extra bit is added to the end of the memory and steered appropriately to replace a defective bit in the memory. This bit redundancy is sometimes called column redundancy because it is orthogonal to row redundancy. Each bit of a memory is steered to one or more columns of data, depending on bit decode. For example, in a memory that has a bit decode of 8, each bit represents 8 columns of data. When a defective bit is replaced with a redundant bit, all 8 columns of data would be replaced.
As memory systems have grown larger, having one redundant bit for the entire memory system has become inadequate. As the number of bits has grown, the redundant bit must serve an ever increasing number of bits thereby increasing the chances that the memory will be defective because there will be more than one defective bit. Thus it is desired to have more than one redundant bit in large memories. Each redundant bit will be assigned to a group of bits called a redundancy region. Each redundant bit can only replace a defective bit within its region.
Also as memory systems have grown larger, memory performance has been improved by dividing the memory system into subsets of memory called local sections, each with their own redrivers of the main signal lines. Each local section of the memory system can be accessed simultaneously, but the redrivers require special addressing schemes. Because these larger memory systems require more than one redundant bit, and because redrivers are typically oriented along a column of memory, rather than a row, the special addressing requirements of the local redriver system prevent the border between redundant bit regions from occurring at any arbitrary location in the memory.
Also, high performance architecture is defined to have redrivers every fixed number of data bits, with the number of redrivers being added as the number of data bits increases. In such a system, at the end of the array, a “partial” redriver might be needed if the leftover number of bits is not equal to the full multiple of redrivers. Thus, in order to properly incorporate the column redundancy control signals, each side of a redriver must only be part of one redundant region. In other words, a redundant region can not cross redriver boundaries. For example, if an SRAM had 8 data bits per local redriver, then a column redundant region boundary can only fall in multiples of 4 bits such that each half redriver can drive to a separate redundant region or the whole redriver will drive to the same redundant region.